1. Field of the Invention
The present invention relates to an electrostatic protection circuit that diverts a surge voltage applied to a signal line away from the circuit that should be protected.
2. Description of Related Art
In general, a semiconductor integrated circuit (IC) is susceptible to a surge voltage arising due to electrostatic discharge (ESD), and is easily broken by the surge voltage. The surge voltage frequently arises when a human (user), who can store therein static electricity of about 2000 V, treats an IC without taking measures against static electricity.
Typically, in order to protect an IC from the surge voltage, an electrostatic protection circuit that diverts the surge voltage away from the circuit that should be protected is provided in the IC. For example, a signal line and a ground potential line of the IC are connected to each other via a diode. In this case, the diode is turned on when the surge voltage is applied to the signal line, and thus the surge voltage can be diverted into the ground potential line. Alternatively, it is also possible to provide a field effect transistor (FET) between the signal line and the ground potential line instead of the diode and control the FET in the gate-controlled drain avalanche breakdown mode, to thereby divert the surge voltage into the ground potential line.
Furthermore, it is also possible to divert the surge voltage away from the circuit that should be protected by using e.g. metal-oxide-semiconductor (MOS) transistors. FIG. 10 is a diagram showing one example of the circuit arrangement of the electrostatic protection circuit employing MOS transistors. An electrostatic protection circuit 100 shown in FIG. 10 includes an n-type MOS transistor 110 and a p-type MOS transistor 120. The n-type MOS transistor 110 has a gate, source, drain, and p-type semiconductor substrate. The gate, source, and p-type semiconductor substrate of the n-type MOS transistor 110 are connected to a ground line L3, and the drain of the n-type MOS transistor 110 is connected to a signal line L1. The p-type MOS transistor 120 has a gate, source, drain, and n-type semiconductor substrate. The gate, source, and n-type semiconductor substrate of the p-type MOS transistor 120 are connected to a power supply line L2, and the drain of the p-type MOS transistor 120 is connected to the signal line L1. Due to this arrangement, the electrostatic protection circuit 100 does not operate when a signal voltage is applied to the signal line. On the other hand, when a surge voltage is applied to the signal line, the p-type MOS transistor 120 is turned on, or the breakdown of the n-type MOS transistor 110 is caused, depending on the magnitude of the surge voltage. This operation makes it possible to divert the surge voltage away from the circuit that should be protected (refer to Japanese Patent Laid-open No. 2003-133434).